1. Field of the Invention
The present invention generally relates to differential and other amplifiers and, more particularly, to methods of reducing DC offset for low power applications.
2. Background Description
Power supply voltages continue to decrease as technology advances and as applications require lower voltages and longer battery life. DC offsets introduced by device mismatches are therefore becoming a larger percentage of the total power supply, thereby reducing the available dynamic range. Matching components on an integrated circuit is difficult and has not improved as rapidly as technology and power supply scaling. The subject of this invention is a circuit topology or architecture for DC offset cancellation.